What happens when more than 220+ students across three continents are given AI-powered chip design tools and told to build real hardware in just over ten days?
You get 64 ambitious projects spanning financial market detection, implantable medical devices, processor optimization, physics acceleration, real-time audio systems, and more, collectively generating approximately 750,000 lines of Register-Transfer Level (RTL) in less than two weeks.
This year, Cognichip’s university hackathon initiative expanded globally, bringing together students from New York University (including NYU Abu Dhabi), University of Toronto, University of Calgary, Toronto Metropolitan University, Texas A&M Engineering, BITS Pilani, and San José State University.
Across campuses, 60+ teams built ambitious ASIC and FPGA systems over just ten days of hacking. Approximately 750,000 lines of RTL were generated, $6,500 in prizes were awarded, and tiny physical chip tapeouts were allotted to winners. More importantly, something shifted.
Software hackathons are everywhere. AI competitions are growing every semester, yet Integrated Circuit (IC) design is still treated as one of the last frontiers, something complex, gated, and years away from beginner access.
As Vraj Prajapati, IEEE ASIC Director at the University of Toronto, shared:
“As larger hackathon projects become more accessible due to AI, we partnered with Cognichip to target the last frontier, IC Design. Over only 5 days, students were able to design their own ASICs for this hackathon, creating innovative circuits for everything from healthcare to finance.”
That is exactly what we set out to test. Could AI meaningfully lower the barrier to serious silicon design? And if it did, would students actually attempt bold projects?
The answer was yes.
One of our judges, who visited campus on Sunday, shared something that really resonated with the team.He said he witnessed a mindset shift in real time. Engineering education is traditionally structured and sequential. You take foundational courses, then advanced courses, then specialize, then enter the industry, and eventually you build in that domain. It is a framework built around readiness and permission.
During the hackathon, students bypassed that framework entirely. They jumped straight in, with some working in domains they had never studied before and building in spaces they had never touched, yet they designed legitimate hardware systems.
“They went from zero to one,” he said. “And zero to one is the hardest leap, but they did it – quickly. And kept going.”
That shift from waiting to begin to simply beginning is significant for our industry. Cognichip did not remove rigor; it enabled momentum. Students were able to start building on day one, experiment, iterate, and ship functioning architectures within the week.
This year’s projects pushed well beyond traditional classroom exercises. Students designed ASICs and FPGA systems, tackling real-world challenges across finance, healthcare, audio processing, physics simulation, and processor optimization. The range of ambition and technical execution exceeded even the highest expectations.
First place went to NYU, where the team built an RISC-V RV32I processor optimization framework using LLM-guided co-design to improve power, performance, and area. In just days, they achieved a 65% reduction in total power and a 240% increase in efficiency. The system also demonstrated something remarkable: the ability to reconstruct a complete, functional MIPS processor datapath from incomplete RTL fragments, showing how AI can reason through partial hardware systems and push optimization further than traditional workflows.
Second place went to NYU’s Vericade, titled “Learning it by Playing it.” The team gamified Verilog and FPGA learning by writing hardware description code to power progressively complex games on an FPGA board. Using Cognichip’s AI tools to generate and verify RTL and testbenches, they debugged their way to a 100% test pass rate, turning hardware education into an interactive and highly practical system.
Third place went to Texas A&M’s SETH-LLM, which evaluated how well Cognichip’s LLM tools could generate and verify increasingly complex Verilog designs, from an 8-bit ALU to full RISC-V processor cores. The smaller designs were fully successful, while the larger systems exposed real constraints around scale and verification, offering valuable insight into both the current strengths and the evolving frontier of AI-assisted hardware design.
At the University of Toronto, students competed across both the ASIC and FPGA tracks, delivering projects that demonstrated technical depth, real-world relevance, and impressive execution under tight timelines.
In the ASIC track, first place went to NeuroCore, a battery-free implantable ASIC designed to close the feedback loop in Transcranial Magnetic Stimulation (TMS) brain therapy. The system measures magnetic-field distortion in tissue and wirelessly transmits real-time correction commands to the TMS machine, enabling adaptive neural therapy without the need for implanted batteries.
Second place in the ASIC track went to the RTL Accelerator for Grid-Based Physics Simulations team. They developed a custom ASIC that accelerates physics simulations by arranging computation cells in a hardware grid, with each cell directly connected to its neighbors. This architecture reduces latency, enables on-chip convergence checking, and demonstrates how spatial hardware organization can dramatically improve simulation efficiency.
Third place in the ASIC track was awarded to NanoTrade, an ASIC designed to detect financial market crashes in under 100 nanoseconds. By leveraging parallel anomaly monitoring and machine-learning classification directly in hardware, the system can trigger circuit breakers at ultra-low latency, demonstrating how purpose-built silicon can address high-frequency financial risk in real time.
In the FPGA track, first place went to FPGAudio, a real-time FPGA-based audio effects processor. The team built a system capable of applying distortion, echo, and pitch shifting to live microphone input via hardware switches, showcasing both practical signal-processing implementation and seamless hardware control.
Together, the students reflected the same pattern we saw globally: ambitious problem selection, serious architectural thinking, and the ability to move from concept to functioning hardware in just days.
At San José State University, 33 students submitted 13 projects over a single weekend — a 160% increase in submissions over the prior year's event. Teams generated more than 35,000 lines of RTL and 14,000 lines of testbench code across just three days.
First place went to Systolix, who built an AI-powered chip accelerator designed to detect anomalies in real-time sensor data — optimized for low-power medical wearables like ICU monitoring devices. Their design passed all 9 validation tests with zero errors, achieving 0.107W total on-chip power at 100 MHz.
Second place went to Jalebi Fafda Chavna, who built a hardware accelerator targeting the memory bottleneck of attention mechanisms in large language models, making transformer-based AI inference feasible on edge devices without cloud connectivity. Their design passed all 512 functional test cases.
Third place went to RISC Taker — a solo submission — who built a smart cache controller for a RISC-V processor incorporating machine learning-based cache decisions and completed a full RTL-to-GDS physical implementation flow with DRC-clean and LVS-clean results.
Across all campuses, students collectively generated approximately 750,000 lines of RTL in just over ten days, with roughly 50 teams moving from concept to implementation and more than 250 participants collaborating across time zones. NYU’s inclusion of its Abu Dhabi campus reinforced the initiative's truly global nature and aligned closely with our broader vision of distributed, AI-enabled hardware development.
The scale of output was impressive, but what struck us even more was the scale of ambition. Students weren’t choosing safe projects; they were selecting meaningful, complex challenges and using AI as a multiplier.
In just over ten days, students across North America, the Middle East, and Asia demonstrated that hardware innovation does not have to follow the slowest possible path. With the right tools, students can move from curiosity to functioning silicon systems in a matter of days, building confidence along the way.
The most striking takeaway may not be the 750,000 lines of RTL or the 65% power reduction; it may be that students who once believed they needed years of preparation felt empowered to begin immediately—and succeeded.
That shift from waiting to building, from zero to one, is where industries change.
The momentum continues on June 20-21 at Cal Hacks, the world's largest collegiate hackathon, where Cognichip will sponsor and equip the next generation of engineers, builders, and problem-solvers tackling real-world challenges in chip design and AI.
Cognichip is investing in this workforce mindshift and workflow change – tackling it with students one hackathon at a time – powered by our Artificial Chip Intelligence.
