Autonomous verification at every level
From testplan generation to full UVM testbench creation, autonomous RCA and debug, to coverage hole filling — ACI transforms the verification bottleneck into a streamlined, AI-powered workflow.
Verification engineers, DV leads, RTL designers — and more
Seoul, South Korea
Automated verification from testplan to coverage closure.
Verification is the #1 bottleneck
Verification is the single largest consumer of time and resources in modern chip design — engineers spend well over half of every project on it, with verification teams now outnumbering designers 3:1. As designs grow more complex, the verification state space explodes exponentially while constrained-random methods scale far more slowly, so coverage closure keeps slipping. And because verification sits at the tail of the flow, late-found bugs force costly re-spins and schedule slips on the critical path to tape-out. The hard part is no longer building the chip — it’s proving it correct.
Intelligence-driven Functional Closure
ACI ingests and analyzes design specifications to build a complete, formal understanding of functional intent, requirements, and dependencies.
- Itemized functional requirement extraction
- Ambiguity and gray-area detection
- Cross-abstraction dependency mapping
- Coverage-relevant scenario identification
ACI turns design specifications into comprehensive testplans that cover functional, corner-case, and structural scenarios.
- Complete testplan mapped to functional requirements
- Incremental testplan updates for spec changes
- Coverage-directed test strategy
- Automatic priority and risk assessment
Generate production-ready UVM testbenches with coverage models, protocol checkers, directed and constrained-random tests, and assertions.
- Coverage models with cross-coverage
- Protocol-aware checkers
- Constrained-random test sequences
- SystemVerilog assertions for critical properties
ACI continuously authors and runs tests to-purpose, based on hypothesis formation and proof. Not random; intentional, explainable, reasoning-based test authoring.
- Coverage gap analysis and prioritization
- Targeted test tuning
- Automated simulation and regression
- Coverage convergence tracking
When tests fail, ACI automatically classifies the failure, traces signals to root cause, and proposes fixes with simulation-verified correctness.
- ML-powered failure classification
- Waveform-level root cause tracing
- Automated fix generation and verification
From failure to fix, autonomously
ACI's automated RCA pipeline identifies failures, traces signals to their root cause, generates a fix, verifies it in simulation, and runs regression — all without manual intervention. This transforms debug from a weeks-long bottleneck into an hours-long automated process.
Coverage achieved at closure
ACI drives every coverage class — statement, branch, SVA, and covergroup — to closure across diverse blocks, in hours instead of weeks.
Coverage achieved at closure (%)
Case 1 · Atomic ALU
2h 30m
zero to closure
Case 2 · L2 Prefetch
4h 0m
zero to closure
Case 3 · Sensor Control
4h 7m
zero to closure
Case 4 · Crypto Blocks
4h 16m
zero to closure
Case 5 · 400G FEC
11h 0m
zero to closure
Testplan to signoff, in conversation
Mina points ACI at the spec and RTL; it generates a requirement-linked testplan, closes coverage, root-causes and fixes the bugs, then drives structural and functional coverage to a 95% signoff — opening each coverage report right in the chat.
Verification reimagined
Unlike agentic approaches that rely on thin wrappers built around general-purpose LLMs, Cognichip's deep technology investments make ACI the industry's only full-stack AI-enabled design solution.
Traditional Verification
- Manual testplan writing takes weeks
- Hand-coded UVM testbenches with long iteration cycles
- Debug is the #1 bottleneck — days per failure
- Coverage closure requires months of manual effort
With ACI Verification
- Spec-to-testplan generation in hours
- Full UVM environment generated from spec
- Automated RCA closes debug loop in hours
- Autonomous coverage convergence
90%
Coverage achieved autonomously
10x
Faster debug turnaround
50%
Reduction in verification schedule
“Semiconductor design cycles have steadily lengthened over the past several decades, creating a major productivity bottleneck for the industry.”
— Umesh Padval, Managing Partner, Seligman Ventures
Close coverage gaps faster with ACI
Transform your verification workflow from months to days.
Backed by $93M from Seligman, SBI, Mayfield, Lux Capital, and Candou Ventures